The communication age and its appetite for increased data throughput continues to force high bandwidth designs. Technologies such as telecommunications and networking, for example, continue to fuel research and design efforts that facilitate serial data rate capabilities on the order of hundreds of gigabits per second and higher.
As the data rate capability increases, other design specifications, such as clock jitter and propagation delay, constrains the circuit designer in regard to the maximum data rate that is achievable. As the data rate increases, for example, the total jitter budget for a particular design decreases. An Optical Carrier (OC)-192 compliant transceiver, for example, having a data rate capability of 10 gigabits per second (Gbps) is allowed less than 1 picosecond (ps) of total jitter due to random noise, i.e., root mean square (rms), jitter. Further, only 10 ps is allowed for deterministic jitter. Therefore, predicting and reducing jitter induced via power supply and other sources of random noise becomes important in most applications.
High performance clock buffers are often used in communication designs for duplication, distribution, and fan-out of clock signals. Sensitivity to clock jitter is a concern in these applications. In many applications, errors resulting from the accumulation of jitter can significantly interfere with system performance and reliability.
Accumulated jitter has profound effects on systems that employ a single clock that is distributed, or fanned out, over many distribution paths, e.g., clock distribution networks. Fundamental knowledge of the requirements of each branch of a given clock tree design, therefore, can be important in understanding which type of device will perform well in a particular design or application.
Specifically, a detailed understanding of the frequency requirements of each clock branch, phase relationships between each clock branch and the reference clock, and phase relationships between each clock branch and every other clock branch is required. Accuracy requirements of the distributed clock signals for both the short term, e.g., cycle to cycle, and long term, e.g., accumulated over n cycles, should be known. Load and termination of the transmission lines used to propagate the clock signals can also be important in the preservation of waveform integrity.
A primary source of jitter is power supply noise. Power supply noise that exists, for example, at the power supply input of a Phase Locked Loop (PLL) will appear on the output of the PLL as jitter. Power supply induced jitter can be a substantial, though not always constant, contributor to jitter.
Power supply noise manifests itself in various ways, both on the top rail and bottom rail power supplies. An inverter operating from a top rail power supply, for example, may have a threshold voltage equal to half of the top rail power supply magnitude. If the top rail power supply contains a voltage ripple component, then the voltage ripple component causes a shift in the threshold voltage at the input to the inverter, which translates into jitter.
Alternately, bottom rail power supply manifestation of jitter may be caused by ground bounce. When there is a surge of current through the output drivers, for example, the inductance of the leads to the supply planes, e.g., VDD and VSS, have a voltage drop across them that is equal to the product of the inductance of the leads and the derivative of the current surge with respect to time. This raises or lowers the effective bottom rail potential of the device. Series resistance may also be a factor when considering finer geometry processes.
Hence, if the device has an output whose frequency is dependent upon supply voltage, e.g., a Voltage Controlled Oscillator (VCO), the frequency will change due to ground bounce. Additionally, any transistors operating within the device experiences a change in threshold voltage, which may also cause a frequency change. Further, if the device is providing an input to a PLL, then the PLL attempts to correct the frequency change, thus further contributing to jitter at its output.
Requirements such as power supply levels, input and output transition times, and circuit board layout often constrain the design of buffer circuits. It is not typically cost effective, however, to design a buffer circuit for each particular application, which may require specialized power supply regulation. It is desirable, rather, to design a buffer circuit that may be effective in a number of applications having varying speed and process requirements, as well as unknown system parameters, such as power supply noise characteristics. A need exists, therefore, for a buffer circuit that minimizes power supply contribution to jitter, while negating the need for customized power supply regulation.
An apparatus and method that addresses the aforementioned problems, as well as other related problems, are therefore desirable.